The present invention relates generally to integrated circuit (IC) devices and, more particularly, to a semiconductor wafer having a bottom surface that is coated with a protective coating prior to the performance of a wafer dicing, or die singulation, operation.
Currently, in order to remain competitive in the IC industry, IC process engineers must continuously increase device yield per wafer or lot. That is, process engineers seek to increase the number of usable semiconductor devices per wafer. Since any step in the fabrication process may detrimentally affect the IC device yield, process engineers seek to optimize each step and, as a result, reduce the number of lost IC devices for the optimized step.
For example, a conventional dicing, or sawing, process is one fabrication step that is likely to result in a substantial loss of devices. In general, when a wafer is diced, chipping may occur along the dicing edges of the individual IC devices. This chipping may then lead to the formation of cracks throughout the IC device, which cracking may damage the IC device and make the IC device unusable for its intended application. In other words, the chipping results in IC devices that are more vulnerable to stress and more susceptible to damage. As a result of an increase in unusable IC devices due to chipping, the IC device yield per wafer or lot is significantly reduced, and product reliability is compromised.
One type of IC device that may be chipped during the dicing operation is a flip chip device. During the dicing process, the flip chip device is cut away from the other flip chip devices of the wafer. The separated flip chip device may have, for example, rough edges as a result of the dicing process. After the flip chip device is separated from the other flip chip devices, the flip chip device is then packaged and/or mounted to a printed circuit board. As a result of chipping, the flip chip device may suffer various form of damage at any point subsequent to the dicing process. For example, the flip chip device may be damaged while it is being handled prior to mounting or packaging.
FIG. 1 is a side view of a conventional flip chip type device 100. The flip chip 100 includes a die 102 that typically has a plurality of conventionally fabricated IC device structures. These IC device structures may include, for example, transistors and interconnect layers. The die 102 has a top surface 108 that includes bump pads (not shown). Bumps 106 are formed on the bump pads of the top most surface 108. This top surface 108 is opposite a bottom surface 104 of the die 102. The bottom surface 104 is conventionally left bare, or exposed. For example, the bottom surface 104 is bare silicon.
There are many problems associated with a conventional wafer that has conventional devices with exposed bottom surfaces. For example, one problem is the aforementioned chipping during the dicing operation. That is, the exposed bottom surface fails to provide sufficient mechanical protection under certain stress inducing conditions. The exposed bottom surface also fails to provide protection from electrostatic shock or light induced bias for flip chip applications. That is, the devices may have functional problems due to photogenerated carriers when the bottom surface (e.g., 104) of the die (e.g., 102) is exposed to light, or the devices may be subject to an undesirable electrostatic shock during handling of the device subsequent to the dicing operation.
The aforementioned problems all contribute to a decrease in production yield. Consequently, there is a need for an improved wafer that provides a solution to the aforementioned problems. For example, there is a need for an improved wafer that is less susceptible to mechanical stress during and after a dicing operation. Additionally, there is a need for a method for making such an improved wafer.